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40 lines
955 B
40 lines
955 B
/* spi.h - SPI definitions */ |
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/* avr : this port does not use spi yet */ |
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/* values below for another platform-arch */ |
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struct spi_csreg { |
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volatile uint32 cr1; |
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volatile uint32 cr2; |
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volatile uint32 sr; |
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volatile uint32 dr; |
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volatile uint32 crcpr; |
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volatile uint32 rxcrcr; |
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volatile uint32 txcrcr; |
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volatile uint32 i2scfgr; |
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volatile uint32 i2spr; |
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}; |
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/* No SPI0 peripheral, starts from 1*/ |
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#define SPI1_BASE 0x40013000 |
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/* Control register settings */ |
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#define SPI_MSTR 2 |
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#define SPI_ENABLE 6 |
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#define SPI_SSM 9 |
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#define SPI_SSI 8 |
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#define SPI_BIDIMODE 15 |
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#define SPI_BIDIOE 14 |
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/* Status register flags */ |
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#define SPI_BSY 7 // Busy |
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#define SPI_TXE 1 // Transfer buffer empty |
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#define SPI_RXNE 2 // Receive buffer NOT empty |
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/* Baud rate control */ |
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#define BR_FPCLKDIV2 0x00000000 |
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#define BR_FPCLKDIV4 0x00000008 |
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#define BR_FPCLKDIV8 0x00000010 |
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#define BR_FPCLKDIV16 0x00000018 |
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#define BR_FPCLKDIV32 0x00000020 |
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#define BR_FPCLKDIV64 0x00000028
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