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53 lines
2.0 KiB
53 lines
2.0 KiB
/* clock.h */ |
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extern uint32 clktime; /* current time in secs since boot */ |
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extern uint32 count1000; /* ms since last clock tick */ |
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extern qid16 sleepq; /* queue for sleeping processes */ |
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extern int32 slnonempty; /* nonzero if sleepq is nonempty */ |
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extern int32 *sltop; /* ptr to key in first item on sleepq */ |
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extern uint32 preempt; /* preemption counter */ |
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struct am335x_timer1ms { |
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uint32 tidr; /* Identification register */ |
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uint32 res1[3]; /* Reserved */ |
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uint32 tiocp_cfg; /* OCP Interface register */ |
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uint32 tistat; /* Status register */ |
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uint32 tisr; /* Interrupt status register */ |
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uint32 tier; /* Interrupt enable register */ |
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uint32 twer; /* Wakeup enable register */ |
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uint32 tclr; /* Optional features */ |
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uint32 tcrr; /* Internal counter value */ |
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uint32 tldr; /* Timer load value */ |
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uint32 ttgr; /* Trigger register */ |
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uint32 twps; /* Write posting register */ |
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uint32 tmar; /* Match register */ |
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uint32 tcar1; /* Capture register 1 */ |
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uint32 tsicr; /* Synchronous interface control*/ |
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uint32 tcar2; /* Capture register 2 */ |
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uint32 tpir; /* Positive increment register */ |
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uint32 tnir; /* Negative increment register */ |
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uint32 tcvr; /* 1ms control register */ |
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uint32 tocr; /* Overflow mask register */ |
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uint32 towr; /* no. of overflows */ |
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}; |
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#define AM335X_TIMER1MS_ADDR 0x44E31000 |
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#define AM335X_TIMER1MS_IRQ 67 |
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#define AM335X_TIMER1MS_TIOCP_CFG_SOFTRESET 0x00000002 |
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#define AM335X_TIMER1MS_TISTAT_RESETDONE 0x00000001 |
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#define AM335X_TIMER1MS_TISR_MAT_IT_FLAG 0x00000001 |
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#define AM335X_TIMER1MS_TISR_OVF_IT_FLAG 0x00000002 |
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#define AM335X_TIMER1MS_TISR_TCAR_IT_FLAG 0x00000004 |
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#define AM335X_TIMER1MS_TIER_MAT_IT_ENA 0x00000001 |
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#define AM335X_TIMER1MS_TIER_OVF_IT_ENA 0x00000002 |
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#define AM335X_TIMER1MS_TIER_TCAR_IT_ENA 0x00000004 |
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#define AM335X_TIMER1MS_TCLR_ST 0x00000001 |
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#define AM335X_TIMER1MS_TCLR_AR 0x00000002 |
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#define AM335X_TIMER1MS_CLKCTRL_ADDR 0x44E004C4 |
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#define AM335X_TIMER1MS_CLKCTRL_EN 0x00000002
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