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@ -7,125 +7,12 @@ typedef unsigned int size_t;
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#include <stdio.h> |
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// RAFA uint32 __attribute__((aligned(0x100))) intc_vector[92]; /* Interrupt vector */
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/* Each message corresponds to an exception in the vector table. */ |
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char * exception_message(uint8 intnr) { |
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/* RAFA
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E_A "--", |
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E_B "RESET", |
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E_etc "NMI", |
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"HARD FAULT", |
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"MEMMANAGE FAULT", |
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"BUS FAULT", |
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"USAGE FAULT", |
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"RESERVED", |
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"RESERVED", |
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"RESERVED", |
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"RESERVED", |
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"SVC", |
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"DEBUG MONITOR", |
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"RESERVED", |
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"RESERVED", |
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"RESERVED", |
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"RESERVED", |
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"PENDSV", |
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"SYSTICK", |
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"IRQ1", |
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"IRQ2", |
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"IRQ3", |
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"IRQ4", |
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// add more if needed
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*/ |
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// RAFA char * messages[] = {
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const char messages[] PROGMEM = { |
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'A', |
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'B', |
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'C', |
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'D', |
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'E', |
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'F', |
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'G', |
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'H', |
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'I', |
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'J', |
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'K', |
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'L', |
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'M', |
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'N', |
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'N', |
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'N', |
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'N', |
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'O', |
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'P', |
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'Q', |
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'R', |
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'S', |
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'T', |
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// add more if needed
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}; |
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if (intnr < 20) // TODO: strlen
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return pgm_read_word(&messages[intnr]); |
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return "UNKNOWN"; |
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} |
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__attribute__ ((naked)) void * dummy_isr(void) { |
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uint32 * current_sp; |
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/* Test whether system call was invoked from supervisor (use MSP) or
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* user (use PSP) mode */ |
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/* asm volatile (
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"tst lr, #4" "\n\t" |
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"ite eq" "\n\t" |
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"mrseq %0, msp" "\n\t" |
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"mrsne %0, psp" : "=r" (current_sp)); */ |
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/*
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asm volatile ("mrs %0, psp" : "=r" (current_sp)); |
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uint8 nr = *SCB_ICSR & 0xFF; |
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kprintf("EXCEPTION: %s\n", exception_message(nr)); |
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kprintf("STACKFRAME:\n"); |
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for (int i = 0; i < 8; i++) { |
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kprintf("STACK[%d]: %x\n", i, current_sp[i]); |
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} |
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halt();
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*/ |
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} |
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/*------------------------------------------------------------------------
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* initintc - Initialize the Interrupt Controller |
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*------------------------------------------------------------------------ |
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*/ |
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int32 initintc() |
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{ |
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/* System control block */ |
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// STM32 specific: struct scb_csreg *csrptr = (struct scb_csreg *)0xE000ED00;
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/* clear entire IVT location in memory */ |
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// RAFA memset(&intc_vector, 0, (sizeof(uint32) * 92));
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/* set dummy handlers */ |
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for (int i = 1; i <= 64 ; i++) { |
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set_evec(i, (uint32) dummy_isr); |
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} |
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/* Enable memory management, bus and usage fault exceptions handlers
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* If these are not enabled, the processor treats them as a hard |
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* faults. Unpriviliged access will cause a busfault in case no MPU */ |
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// STM32 specific: srptr->shcsr |= (1 << MPUFAULT_EN) | (1 << BUSFAULT_EN) | (1 << USAGEFAULT_EN);
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/* The vector table is intially at 0x0. The vector table can be
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* relocated to other memory locations. We can do this by setting
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* a register in the NVIC called the vector table offset register */ |
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// RAFA // STM32 specific: srptr->vtor = (uint32) &intc_vector;
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return OK; |
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} |
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@ -141,10 +28,6 @@ int32 set_evec(uint32 xnum, uint32 handler)
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return SYSERR; |
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} |
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/* Install the handler */ |
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// STM32 specific: intc_vector[xnum] = handler;
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return OK; |
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} |
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